Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), flash memory, resistance variable memory, such as phase change random access memory (PCRAM) and resistive random access memory (RRAM), and magnetic random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.
Some memory cells, such as flash memory cells, can be 1-transistor (1T) memory cells. An example of a flash memory cell is shown in FIG. 1. The flash memory cell 103 has a stacked gate structure that includes a floating gate 116 capacitively coupled to a control gate 120. The floating gate 116 and control gate 120 are often formed of a polysilicon material and are separated by a dielectric material 118 (e.g., an interpoly dielectric), which can be about 150 to 300 angstroms thick.
The flash cell 103 includes an N+ drain region 112 and an N+ source region 110 inside a well region of a P-substrate 101. The cell 103 also includes a tunnel oxide layer 114 overlying a channel region of the substrate 101 (e.g., between the floating gate 116 and the channel region of the substrate 101). The tunnel oxide layer 114 is often silicon dioxide and can be about 70 to 120 angstroms thick.
In operation, the cell 103 can be programmed by grounding the source terminal, applying a 5 to 10 volt signal to the drain 112 (e.g., via a bit line not shown), and applying a high programming voltage of, for example, 18 to 20 volts to control gate 120. The high voltage applied to the control gate 120 creates a high electric filed across tunnel oxide 114 generating hot electrons in the channel with enough energy to cross the tunnel oxide 114. These hot electrons are then trapped in the floating gate 116, resulting in a higher threshold voltage for the transistor, which can correspond to the cell 103 being programmed into an OFF (e.g., non-conducting) state.
The cell 103 can be erased by grounding the control gate 120 and the drain region 112 and applying a high voltage (e.g., 18 to 20 volts) to the source region 110 or the P-well region of substrate 101. The large voltage difference causes the trapped electrons on the floating gate 116 to tunnel through the thin oxide layer 114 by a mechanism known as Fowler-Nordheim tunneling.
1-transisotor memory cells such as flash memory cell 103 have a number of drawbacks with regard to performance. For instance, the relatively high voltage (e.g., 18 to 20V) used to program and/or erase the cell via tunneling through the tunnel oxide 114 can reduce the ability to scale the memory cell 103. Also, the relatively thin tunnel oxide 114 can degrade over time (e.g., over multiple program/erase cycles), which can effect the reliability of the cell 103.